Japanese Patent Application No. 2001-378988 filed on Dec. 12, 2001 is hereby incorporated by reference in its entirety.
The present invention relates to a semiconductor memory device such as an SRAM and an electronic instrument using the same, particularly to a semiconductor memory device capable of preventing leakage current from being generated due to a short circuit in a pattern inside a memory cell, for example, and an electronic instrument using the same.
In this type of semiconductor memory devices, when a defective memory cell is found in the inspection processes, the repair processes are conducted in which the defective memory cell is replaced by a redundant memory cell. For example, a short circuit is generated at the place indicated by a cross between nodes in a memory cell 110 shown in FIG. 5. In this case, a sub word line SWL connected to the defective memory cell 110 where the short circuit has been generated is not selected.
However, even though the sub word line SWL is in the state not to be selected, the short circuit indicated by the cross is not eliminated. Therefore, a leakage current passing through a path A is inevitably generated between a Vdd line 140 and a Vss line 142 due to the generation of the short circuit.
In addition, this type of the semiconductor memory devices has a challenge to satisfy both the realization of high integration and high speed. When the realization of high integration is achieved, the number of memory cells in the longitudinal and transverse directions is increased.
When there are a large number of memory cells in the transverse direction, the length of a single Vdd line 140 becomes longer and the number of memory cells connected thereto becomes greater. Thus, the load resistance and the load capacity of the single Vdd line 140 become greater.
It will be no problem when the voltage of the Vdd line 140 is always constant. However, in the mode to hold data of memory cells 110 at low voltage, such as called retention mode, the voltage supplied to the Vdd line 140 is lowered. Therefore, particularly when the retention mode is cancelled to return to the normal operation mode, the time required to return the Vdd line 140 to have the Vdd voltage becomes longer. Accordingly, the time is required until starting data write after canceling the retention mode, and thus the semiconductor memory device cannot be operated at high speed.
The present invention may provide a semiconductor memory device capable of preventing leakage current from being generated with a defective memory cell and an electronic instrument using the same.
The present invention may also provide a semiconductor memory device capable of satisfying both the realization of high integration and high speed and an electronic instrument using the same.
A semiconductor memory device according to one aspect of the present invention includes a plurality of word lines extending along a first direction; a plurality of memory cells to be selected by each of the word lines, the memory cells being disposed along the first direction and a second direction, the first and second directions intersecting each other; and a plurality of sub power source lines extending along the first direction, each of the sub power source lines supplying a power source voltage to the memory cells arranged along the first direction.
A main power source line supplies the power source voltage to the sub power source lines, and a plurality of fuse elements connects the main power source line to the sub power source lines. A predetermined number of the sub power source lines are connected by one of a plurality of common connecting sections, each of the common connecting sections being provided at one end of the predetermined number of the sub power source lines and being connected to the main power source line through each of the fuse elements.
According to this aspect of the present invention, when a defect is detected in a memory cell connected to any one of the sub word lines, the supply of the power source voltage to a predetermined number of the sub word lines commonly connected to the common connecting section with the defective sub word line is blocked by cutting the corresponding fuse element. This can prevent the leakage current along the path A shown in FIG. 5, or the like.
The leakage current along the path A shown in FIG. 5 can be prevented by blocking the power supply to the single sub power source line connected to the defective memory cell. However, to this end, a fuse element needs to be connected to every sub power source line. Usually, about 2000 lines of sub power source lines, for example, are disposed for a single memory array. Since the number of fuse elements increases too much, it is difficult to dispose the fuse element at every single sub power source line arranged at a predetermined pitch.
In this aspect of the present invention, one fuse element is disposed for a predetermined number of the sub power source lines. Accordingly, a common connecting section is provided to bind predetermined number of the sub power source lines at one ends.
The semiconductor memory device can further comprise a plurality of redundant word lines extending along the first direction, and a plurality of redundant memory cells to be selected by each of the redundant word lines, the redundant memory cells being disposed along the first direction and the second direction. In this case, the number of the predetermined number of the sub power source lines commonly connected to each of the common connecting sections may be equal to the number of the redundant word lines, the redundant word lines being replaced when a defective memory cell is detected in the memory cells.
In this configuration, all the memory cells connected to the predetermined number of the sub power source lines commonly connected to the common connecting section can be replaced by the redundant memory cells. Therefore, the power supply is blocked to all the memory cells that will not be selected by the replacement, whereby the entire leakage including the leakage current indicated by a path A shown in FIG. 5 can be prevented.
In this semiconductor memory device, the word lines can have a plurality of main word lines and a plurality of sub word lines, the sub word lines being subordinate to each of the main word lines, each of the sub word lines being connected to the memory cells arranged in the first direction.
Accordingly, one aspect of the invention can also be adapted to the type of semiconductor memory devices that word lines are divided into main and sub word lines. In this case, the sub word lines can be set to have the length of a single sub word line stayed in a block when a memory cell array is divided into blocks in the first direction.
Therefore, in the case of having the main and the sub word lines, the number of the predetermined number of the sub power source lines commonly connected to each of the common connecting sections may be equal to the number of the sub word lines subordinate to each of the main word lines.
This semiconductor memory device can further comprise a plurality of redundant main word lines extending along the first direction, a plurality of redundant sub word lines subordinate to each of the redundant main word lines, and a plurality of redundant memory cells to be selected by each of the redundant sub word lines, the redundant memory cells being disposed along the first direction and the second direction.
In this case, the number of the predetermined number of the sub power source lines commonly connected to each of the common connecting sections may be equal to the number of the redundant sub word lines subordinate to each of the redundant main word lines. In this manner, one main word line and the sub word lines subordinate thereto are replaced as one unit with one redundant main word line and the redundant sub word lines subordinate thereto, so as to repair a defective memory cell. On this account, power does not need to be supplied to the predetermined number of the sub power source lines connected to all the memory cells that will not be selected by the replacement. The power supply is thus blocked, whereby the leakage current carried along the path A shown in FIG. 5 can be prevented.
In this semiconductor memory device, each of the sub power source lines can be formed of at least a single metal layer. The sub power source lines becomes longer by the realization of high integration of the memory cells, whereby the load resistance is increased. The load capacity is also increased because a large number of memory cells are connected thereto. On this account, the sub power source lines are formed of a metal layer having a low sheet resistance, whereby the wiring resistance is lowered.
The metal layer can comprise upper and lower metal layers. In this case, the main power source line and each of the fuse elements can be formed of the upper metal layer, and each of the sub power source lines can be formed of the lower metal layer. Particularly, the fuse element is formed of the upper metal layer so that an opening is formed in a passivation film thereabove and a laser is irradiated to cut the fuse element through the opening.
In this semiconductor memory device, each of the sub power source lines can include a first sub power source line and a second sub power source line, the first sub power source line being located below the second sub power source line, an interlayer dielectric being formed between the first and second sub power source lines. In this case, the second sub power source line may be formed of a metal layer and connected to each of the common connecting sections. In addition, the first sub power source line may be formed of a layer having higher resistance than the second sub power source line and connected to the memory cells arranged along the first direction. Then, the first sub power source line may be connected to the second sub power source line through a via. In other words, the first sub power source line of high resistance is backed by the second sub power source line of a metal layer, whereby the load resistance of the sub power source line can be reduced.
In this semiconductor memory device, a power source voltage Vdd can be supplied to the main power source line and the sub power source lines in a normal operation mode in which the memory cells are read and written, and a voltage lower than the power source voltage can be supplied to the main power source lines and the sub power source lines in a retention mode in which data stored in the memory cells is held at a low voltage.
In returning to the normal operation mode from the retention mode, when the load resistance of the sub power source lines is small, the time for charging up to the power source voltage Vdd can be shortened. Accordingly, the time between canceling the retention mode and starting data writing, for example, can be shortened and high-speed operation becomes possible.
According to another aspect of the present invention, an electronic instrument comprises the above described semiconductor memory device. The electronic instrument, such as portable devices, of low power consumption can be realized by installing the semiconductor memory device capable of preventing the leakage current.